rohd verification framework

the rohd verification framework (rohd-vf) is a verification framework built upon the rapid open hardware development (rohd) framework. it enables testbench organization in a way similar to uvm. a key motivation behind it is that hardware testbenches are really just software, and verification engineers should be empowered to write them as great software. the rohd verification framework enables development of a testbench in a modern programming language, taking advantage of recent innovations in the software industry.

with rohd and rohd-vf, your testbench and hardware execute natively in dart in a single fully-debuggable process. there is no black-box vendor simulator to interact with, just execute your software. you can leverage the cosimulation functionality of rohd to build rohd-vf testbenches for designs that include (or are entirely) written in other languages (e.g. systemverilog).

the rohd verification framework does not implement exactly the same api as uvm. rather, it takes some key concepts that are useful for testbench design and omits features that are rarely used, present to work around language limitations in systemverilog, encourage outdated or overly opinionated design patterns, or otherwise don’t add significant value. the rohd verification framework eliminates the macros and boilerplate that are associated with uvm.

the rohd verification framework offers a simple, clean, and scalable methodology for developing testbenches with moderate to high complexity. verifying a very small and simple design may be easier with a “peek & poke” type methodology using logic.value and logic.inject directly on the dut interfaces. a “peek & poke” methodology for a larger, more complex design is usually not a scalable approach. the “startup cost” associated with building a full testbench with the rohd verification framework is drastically lower than one might traditionally expect if they had experience with uvm in the past.

testbenches

a testbench is software used to interact with and test a device under test (dut). rohd verification framework testbenches are organized in a modular and extenable way using simple base classes which have specific roles. the diagram below shows what a typical testbench might look like. more details about each of the objects in the testbench are described below. this should look very familiar if you’ve used uvm.

example

dive right in with a full example testbench for a counter. the example includes monitors, a driver, a sequencer, an agent, an env, a test, the same dut as the rohd counter example, a sequence with sequenceitems, a scoreboard, and a main function to kick it all off, all in a single commented file.

constructing objects

the rohd verification framework does not come with a built-in “factory” (like uvm) for constructing components in the testbench. instead, objects can just be constructed like any other object. it is a good idea to build a testbench with modularity and configurability in mind so that behavior can be easily changed depending on the desired test. there is no restriction against using a factory design pattern to build a testbench if that’s the right approach for a specific situation. you also might be interested in using other approaches, such as dependency injection. rohd-vf doesn’t push a strong opinion here.

phases

a lot of setup for the testbench can occur in the constructor of the object. rohd-vf comes with some phasing (similar to uvm) to help configure, connect, and run a testbench in coordinated steps. every component goes through phases.

• the constructor
  • clearly enumerate what is required to build the component as part of the constructor parameters.
  • construct any sub-components.
• void build()
  • a function which gets called when the test is started, but before the simulator is running.
• future<void> run(phase phase)
  • a time-consuming function which starts executing when the test and simulator are running.
  • use phase to create objections.
• void check()
  • a function that gets called at the end of the simulation, for checking the end state for correctness.

components

a component is an object which holds a fixed hierarchical position in the testbench. the hierarchy is determined at construction time by passing information about each component‘s parent (null if no parent / top level). all of the below classes extend component. you can build your testbench extending these subclasses of component or directly extend component.

monitor

a monitor is responsible for watching an interface and reporting out interesting events onto an output stream. this bridges the hardware world into an object that can be manipulated in the testbench. many things can listen to a monitor, often logging or checking logic.

driver

a driver is responsible for converting a sequenceitem into signal transitions on a hardware interface. the driver accepts incoming items from a sequencer.

sequencer

a sequencer accepts sequenceitems from stimulus sources (e.g. sequences) and determines how to pass them to the appropriate driver(s). the default behavior of a sequencer is to directly pass them to the driver immediately, but they can be more complex than that.

agent

the agent is a wrapper for related components, often which all look at a single interface or set of interfaces. typically, an agent constructs some monitors, drivers, and sequencers, and then connects them up appropriately to each other and interfaces.

env

the env is a wrapper for a collection of related components, often each with their own hierarchy. envs are usually composed of agents, scoreboards, configuration & coordination logic, other smaller envs, etc.

test

a test is like a top-level testing entity that contains the top testbench env and kicks off sequences. only one test should be running at a time. the test also contains a central random object to be used for randomization in a reproducible way.

stimulus

sending stimulus through the testbench to the device under test is done by passing sequenceitems through a sequencer to a driver.

sequenceitem

a sequenceitem represents a collection of information to transmit across an interface. a typical use case would be an object representing a transaction to be driven over a standardized hardware interface.

sequence

a sequence is a modular object which has instructions for how to send sequenceitems to a sequencer. a typical use case would be sending a collection of sequenceitems in a specific order.

virtual sequencers & sequences

it is possible to create a “virtual” sequencer whose role is to distribute sequences or sequenceitems to other sub-sequencers. sequences that run on a “virtual” sequencer are called “virtual” sequences. there’s no special support in rohd-vf for these, but the standard sequencer and sequence objects can be easily used for this purpose.

logging

rohd-vf uses the dart logging package for all logging. it comes with a variety of verbosity levels and excellent customizability.

the test object contains settings for killlevel and faillevel which will, respectively, immediately end the test or cause a test failure when the simulation finishes running. these levels are associated with the levels from the logging package.

to log a message from any rohd-vf object or component, just use the inherited logger object.

2021 november 9
author: max korbel <[email protected]>

copyright (c) 2021 intel corporation
spdx-license-identifier: bsd-3-clause